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1 rev. 4110g?aero?07/03 features up to 1.6m used gates and 596 pads with 3.3v, 3v and 2.5v libraries high speed - 180 ps gate delay - 2 input nand, fo = 2 (nominal) system level integration technology cores on request memories: sram and tpram, gate level or embedded, with edac i/o interfaces: ? 5v tolerant/compliant (s) or 3v (r) matrix options ? cmos, lvttl, lvds, pci, usb, etc. ? output currents programmable from 2 to 24 ma, by step of 2 ma ? cold sparing buffers (2 a max. leakage current at 3.6v worst case mil temp.) 250 mhz pll (on request), 220 mhz lvds and 800 mhz max. toggle frequency at 3.3v deep submicron cad flow latch-up immune; 300k rads total dose capability; seu free cells; 4000v esd protection qml q and v with smd 5962-01b01, rha (100 krads) description the MH1RT gate array and embedded array families from atmel are fabricated on a radiation tolerant 0.35 micron cmos process, with up to 4 levels of metal for intercon- nect. this family features arrays with up to 1.6 million routable gates and 596 pads. the high density and high pin count capabilities of the MH1RT family, coupled with the ability to embed cores or memories on the same silicon, make the MH1RT series of arrays one of the best choices for system level integration. the MH1RT series is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. verilog ? , dft ? , synop- sys ? and vital are the reference front end tools. the cadence ? ?logic design planner? floor planning associated with timing driven layout provides an efficient back end cycle. the MH1RT series comes as a dual use of the mh1 series, adding: - through process changes, the 100 mev latch-up immunity and the 300k rads total dose capability as required by most space programs - through cells relayout, an seu immunity allowing to seu harden only where it is nec- essary with respect to function requirements with a background of 15 years experience, the MH1RT series comes as the atmel 7th generation of asic series designed for radiation hardened applications. rad hard 1.6m used gates 0.35 m cmos sea of gates/ embedded array MH1RT
2 MH1RT 4110g?aero?07/03 notes: 1. nominal 2 input nand gate fo = 2 at 3.3v. design design systems supported atmel supports several major software systems for design with complete macro cell libraries, as well as utilities for checking the netlist and estimated pre-route delay simulations. the following design systems are supported: table 1. list of available MH1RT matrices device number typical routable gates max pad count max i/o count gate speed (1) max. sites count mh1099e 519,000 332 324 180 ps 920,385 mh1156e 764,000 412 404 180 ps 1,447,975 mh1242e 1,198,000 512 504 180 ps 2,275,377 mh1332e 1,634,000 596 588 180 ps 3,098,804 table 2. supported design systems system available tools cadence verilog-xl ? - verilog simulator logic design planner ? - floorplanner buildgates ? - synthesis (ambit) mentor/model tech modelsim verilog and vhdl (vital) simulator dft- scan insertion and atpg, bist synopsys ? design compiler? - synthesis primetime ? - static path formality ? - equivalence checking
3 MH1RT 4110g?aero?07/03 design flow and tools atmel?s design flow for gate array/embedded array is structured to allow the designer to consolidate the greatest number of system components possible onto the same sili- con chip, using available third party design tools. atmel?s cell library reflects silicon performance over extremes of temperature, voltage, and process, and includes the effects of metal loading, inter-level capacitance, and edge rise and fall times. the design flow includes clock tree synthesis to minimize skew and latency. rc extraction is performed on final design database and incorporated into the timing analysis. the typical gate array/embedded array design flow, shown on page 4, provides a pic- torial description of the typical interaction between atmel?s gate array/embedded array design staff and the customer. atmel will deliver design kits to support the customer?s synthesis, verification, floorplanning, and scan insertion activities. tools such as syn- opsys synthesis, cadence and mentor logic simulators are used, and many others are available. should a design include embedded memory or an embedded core, atmel needs to understand the partition of the array, and define the location of the memory blocks and/or cores (preliminary place and route) so that an underlayer layout model can be created (base wafer). following a preliminary design review, so called logic review, the design is routed, and post-route rc data is extracted. following post-route verification and a final design review, so called design review, the design is taped out for fabrication. the purpose of these reviews is to check the conformity of the design to atmel rules, and acknowledge it in formal documents.
4 MH1RT 4110g?aero?07/03 figure 1. typical gate array/embedded array design flow atmel atmel atmel atmel atmel atmel atmel atmel rev.1.6 - 07/2003 joint atmel customer design kit delivery base wafer definition base wafer creation base wafer base wafer fabrication tape out metallization layers masks generation fab., assembly and test design review place & route and clock tree post-route verification logic review pre-route verification database acceptance database handoff preliminary place & route floorplan scan insertion design synthesis kickoff functional and static path sims
5 MH1RT 4110g ? aero ? 07/03 pin definition requirements the corner pads are reserved for power and ground only. all other pads are fully pro- grammable as input, output, bidirectional, power or ground. when implementing a design with 5v tolerant buffers, one buffer site must be reserved for the v dd5 pin, which is used to distribute power to the buffers. figure 2. gate array figure 3. embedded array i/o site: pad and sub- sections the i/o sites can be configured as input, output, 3-state output and bidirectional buffers, each with pullup or pulldown capability, if required, by utilizing their corresponding sub- section. bidirectionnal buffers are the result of an input and output buffers placed in adjacent sub-sections in the same i/o site. special buffers may require multiple i/o sites. oscillators require 2 i/o sites, each power and ground pin utilizes one i/o site. pci buffers pci compatible input and output buffers are available for each bias voltage, 3v and 5v. lvds buffers each lvds buffer uses 2 i/o sites. lvds drivers are specific for each bias voltage and require one external current bias resistor per chip; lvds receiver is the same for all bias voltages and requires 1 external line matching 100 ? resistor per receiver. cold sparing it is the use of twice the same chip, a1 and a2, a1 on and a2 off, with all signal pins/pads connected by pairs, a1i1 with a2i1, a101 with a201,... sram core core standard gate array architecture
6 MH1RT 4110g ? aero ? 07/03 during this mode operation: ? the chip off must survive and operate when turned on without functional, ac, dc or reliability impact, ? the current pulled by the off chip must be limited to a low value: atmel specification for their dedicated cold sparing buffers is 2 a worst case by signal pins/pads. for any other operation mode, refer to maximum ratings. memory blocks memory blocks can be either synthesized on gates (when smaller than 8 bits) or com- piled and embedded in the array itself. various combinations of through flow or bus watch edacs, 4, 8, 16 and 32 bit wide, can be used to alleviate the effect of seu induced errors.
7 MH1RT 4110g ? aero ? 07/03 asic design translation atmel has successfully translated existing designs from most major asic vendors (lsi logic ? , motorola ? , smos ? , oki ? , nec ? , fujitsu ? , ami ? and others) into the gate arrays. these designs have been optimized for speed and gate count and modified to add logic or memory, or replicated for a pin-to-pin compatible, drop-in replacement. design entry design entry is performed by the customer using an atmel asic library. a complete netlist and vector set must then be provided to atmel. upon acceptance of this data set, atmel continues with the standard design flow. fpga and pld conversions atmel has successfully translated existing fpga/pld designs from most major ven- dors (xilinx ? , actel ? , altera ? , amd ? and atmel) into the gate arrays. there are four primary reasons to convert from an fpga/pld to a gate array. conversion of high vol- ume devices for a single or combined design is cost effective. performance can often be optimized for speed or low power consumption. several fpga/plds can be com- bined onto a single chip to minimize cost while reducing on-board space requirements. finally, in situations where an fpga/pld was used for fast cycle time prototyping, a gate array may provide a lower cost answer for long-term volume production. cell library atmel's MH1RT series gate arrays make use of an extensive library of macro cell struc- tures, including logic cells, buffers and inverters, multiplexers, decoders, and i/o options. soft macros are also available. the MH1RT series pll operates at frequencies of up to 250 mhz with minimal phase error and jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip to chip synchronization. these cells are well characterized by use of spice modeling at the transistor level, with performance verified on manufactured test arrays. characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately pre- dicts the performance of the finished product. cells number of cells logic cells 95 i/o buffers 3v or 2.5v or 3.3v 5v tolerant 5v compliant 110 36 70 specific cells lvds, pci 11 seu hardened cells 9 cold sparing 63
8 MH1RT 4110g ? aero ? 07/03 electrical characteristics absolute maximum ratings dc characteristics applicable over recommended operating temperature and voltage range unless otherwise noted. operating ambient temperature .........-55 c to +125 c *note: stresses beyond those listed under "absolute maxi- mum ratings ? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature........................... -65 c to +150 c maximum input voltage vdd ...+0.5v and vcc + 0.5v maximum 3.3v operating voltage................. 4v (vdd) maximum 5v operating voltage.................... 6v (vcc) table 3. 2.5v dc characteristics symbol parameter buffer test condition min. typ max. units t a operating temperature all -55 25 125 c v dd supply voltage all 2.3 2.5 2.7 v i il low-level input current pull-up resistors pru1 (1) pull down resistor prd1 cmos v in = v ss -1 70 -5 1 230 5 a i ih high level input current pull-up resistors pru1 pull down resistor prd1 (2) cmos v in = v dd ( max.) -1 -5 70 1 5 540 a ioz high impedance state output current all vin = vdd or vss, vdd = vdd (max.) no pull resistor -1 ? 1 a vil low level input voltage cmos 0.3vdd v pci 0.325vdd schmitt level 0.62 vih high level input voltage cmos 0.7 vdd v pci 0.475vdd schmitt level 1.56 delta v cmos hysterisis 0.42 v iics cold sparing leakage input current picz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a iocs cold sparing leakage output current poxxz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a vcsth (3) supply threshold of cold sparing buffers poxxz iocs = 100 a 0.5 v v ol low-level output voltage (4) po11 i ol = 0.8 ma, vdd = vdd (min.) 0.4 v
9 MH1RT 4110g ? aero ? 07/03 applicable over recommended operating temperature and voltage range unless otherwise noted. voh high level output voltage (5) po11 ioh = -0.6 ma, vdd = vdd (min.) 2 v ios output short circuit current iosn iosp po11 po11 vdd = vdd (max.), vout = vdd vouy = vss 15 8 ma iccsb leakage current per cell vdd = vdd (max.) 0.27 4 na iccop dynamic current per gate vdd = vdd (max.) 0.3 w/mhz 1. for standard pull-ups: pru (#), # = {1-31} index for ron: ron = # x ro where ro = 19 k ? typ, 30 k ? max., 12 k ? min. 2. for standard pull-downs: prd (#), # = {1-31} index for ron: ron = # x ro where ro = 11 k ? typ, 30 k ? max., 5 k ? min. 3. guaranteed not tested 4. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to decimal x io = p and n-channel output drive io = 0.8 ma for standard buffers (including cold sparing) measured at vol = 0.4v 5. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to decimal x io = p and n-channel output drive io = -0.6 ma for standard buffers (including cold sparing) measured at voh = 2v table 3. 2.5v dc characteristics (continued) symbol parameter buffer test condition min. typ max. units
10 MH1RT 4110g ? aero ? 07/03 . table 4. 3v dc characteristics symbol parameter buffer test condition min. typ max. units t a operating temperature all -55 25 125 c v dd supply voltage all 2.7 3.0 3.3 v i il low-level input current pull-up resistors pru1 (1) pull down resistor prd1 1. for standard pull-ups: pru (#), # = {1-31} index for ron: ron = # x ro where ro = 15 k ? typ, 25 k ? max., 10 k ? min. cmos v in = v ss -1 108 -5 1 330 5 a i ih high level input current pull-up resistors pru1 pull down resistor prd1 (2) 2. for standard pull-downs: prd (#), # = {1-31} index for ron: ron = # x ro where ro = 9 k ? typ, 25 k ? max., 4 k ? min. cmos v in = v dd( max.) -1 -5 108 1 5 825 a ioz high impedance state output current all vin = vdd or vss, vdd = vdd (max.) no pull resistor -1 1 a vil low level input voltage cmos 0.8 v pci 0.325vdd schmitt level 0.72 vih high level input voltage cmos 2 v pci 0.475vdd schmitt level 1.89 delta v cmos hysterisis 0.53 v iics cold sparing leakage input current picz vdd = vss = 0v vin = 0 to 3.3v -2 ? -2 a iocs cold sparing leakage output current poxxz vdd = vss = 0v vin = 0 to 3.3v -2 ? -2 a vcsth (3) 3. guaranteed not tested. supply threshold of cold sparing buffers poxxz iocs = 100 a ? 0.5 ? v v ol low-level output voltage (4) 4. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to decimal x io = p and n-channel output drive io = 1 ma for standard buffers (including cold sparing) measured at vol = 0.4v po11 i ol = 1 ma, vdd = vdd(min.) ?? 0.4 v ?? voh high level output voltage (5) po11 ioh = -0.8 ma, vdd = vdd(min.) 2.4 ?? v ios output short circuit current iosn iosp po11 po11 vdd = vdd(max.), vout = vdd vouy = vss ?? 21 12 ma iccsb leakage current per cell ? vdd = vdd(max.) ? 0.6 5 na iccop dynamic current per gate ? vdd = vdd(max.) ?? 0.5 w/mhz
11 MH1RT 4110g ? aero ? 07/03 5. for output buffers po (1-c) (1-c):1-c: hex value: convert hex to decimal x io = p and n-channel output drive io = -0.8 ma for standard buffers (including cold sparing) measured at voh = 2.4v table 5. 3.3v dc characteristics symbol parameter buffer test condition min. typ max. units t a operating temperature all -55 25 125 c v dd supply voltage all 3 3.3 3.6 v i il low-level input current pull-up resistors pru1 (1) pull down resistor prd1 cmos v in = v ss -1 120 -5 1 400 5 a i ih high level input current pull-up resistors pru1 pull down resistor prd1 (2) cmos v in = v dd( max.) -1 -5 150 1 5 900 a ioz high impedance state output current all vin = vdd or vss, vdd = vdd(max.) no pull resistor -1 1 a vil low level input voltage cmos 0.8 v pci 0.325vdd schmitt level 0.8 vih high level input voltage cmos 2 v pci 0.475vdd schmitt level 2 delta v cmos hysterisis 0.61 v iics cold sparing leakage input current picz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a iocs cold sparing leakage output current poxxz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a vcsth (3) supply threshold of cold sparing buffers poxxz iocs = 100 a 0.5 v v ol low-level output voltage (4) po11 i ol = 2 ma, vdd = vdd(min.) 0.4 v voh high level output voltage (5) po11 ioh = -1.8 ma, vdd = vdd(min.) 2.4 v ios output short circuit current iosn iosp po11 po11 vdd = vdd(max.), vout = vdd vouy = vss 23 13 ma iccsb leakage current per cell vdd = vdd(max.) 0.7 5 na iccop dynamic current per gate vdd = vdd(max.) 0.63 w/mhz 1. for standard pull-ups: pru(#), # = {1-31} index for ron: ron = # x ro where ro = 14 k ? typ, 25 k ? max., 9 k ? min. 2. for standard pull-downs:prd(#), # = {1-31} index for ron: ron = # x ro where ro = 8 k ? typ, 20 k ? max., 4 k ? min. 3. guaranteed not tested. 4. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to k ? x io = p and n-channel output drive io = 2 ma for standard buffers (including cold sparing) measured at vol = 0.4v
12 MH1RT 4110g ? aero ? 07/03 applicable over recommended operating temperature and voltage range unless otherwise noted. 5. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to k ? x io = p and n-channel output drive io = -1.8 ma for standard buffers (including cold sparing) measured at voh = 2.4v table 6. 5v dc characteristics symbol parameter buffer test condition min. typ max. units t a operating temperature all -55 25 125 c v dd supply voltage 5v tolerant 3.0 3.3 3.6 v v cc supply voltage 5v compliant 4.5 5 5.5 v i il low-level input current pull-up resistors pru1 (1) pull down resistor prd1 cmos v in = v ss -1 180 -5 1 690 5 a i ih high level input current pull-up resistors pru1 pull down resistor prd1 (2) cmos v in = v dd( max.) -1 -5 30 1 5 400 a ioz high impedance state output current all vin = vdd orvss,vdd=vdd(max no pull resistor -1 1 a vil low level input voltage picv, picv5 0.8 v pci 0.325vdd schmitt level 1.1 0.8 vih high level input voltage picv, picv5 2 v pci 0.475vdd schmitt level 2 1.7 iics cold sparing leakage input current picz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a iocs cold sparing leakage output current poxxz vdd = vss = 0v vin = 0 to 3.3v -2 -2 a vcsth (3) supply threshold of cold sparing buffers poxxz iocs = 100 a 0.6 v v ol (4) low voltage/2.5v range low voltage/3.0v range low voltage/3.3v range low voltage/2.5v range low voltage/3.0v range low voltage/3.3v range po11v po11v po11v po11v5 po11v5 po11v5 iol = 0.5 ma iol = 0.6 ma iol = 1.2 ma iol = 1.1 ma iol = 1.3 ma iol = 1.5 ma 0.4 v
13 MH1RT 4110g ? aero ? 07/03 lvds driver dc and ac characteristics applicable over recommended operating temperature and voltage range unless otherwise noted. voh (5) low voltage/2.5v range low voltage/3.0v range low voltage/3.3v range low voltage/2.5v range low voltage/3.0v range low voltage/3.3v range po11v po11v po11v po11v5 po11v5 po11v5 ioh = 0.5 ma ioh = 0.6 ma ioh = 1.2 ma ioh = 1.1 ma ioh = 1.3 ma ioh = 1.5 ma 2 2.4 2.4 2.4 2.4 2.4 v ios output short circuit current iosn iosp po11v po11v vdd = vdd(max.), vout = vdd vouy = vss 28 17 ma 1. for 5v tolerant/compliant pull-ups: pru(#), # = {1-31} index for ron: ron = # x ro where ro = 14 k ? typ, 25 k ? max., 8 k ? min. 2. for 5v tolerant/compliant pull-downs: prd(#), # = {1-31} index for ron: ron = # x ro where: ro = 19 k ? typ, 45 k ? max., 9 k ? min. in 3.3v range, ro = 23 k ? typ, 55 k ? max., 11 k ? min. in 3v range, ro = 36 k ? typ, 80 k ? max., 17 k ? min. in 2.5v range, 3. guaranteed not tested. 4. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to k ? x io = p and n-channel output drive io = 1.5 ma for compliant buffers (including cold sparing) in 3.3v range (vcc = 4.5v ) measured at vol = 0.4v io = 1.3 ma for compliant buffers (including cold sparing) in 3.0v range (vcc = 4.5v ) measured at vol = 0.4v io = 1.1 ma for compliant buffers (including cold sparing) in 2.5v range (vcc = 4.5v ) measured at vol = 0.4v 5. for output buffers po (1-c) (1-c): 1-c: hex value: convert hex to k ? x io = p and n-channel output drive io = 1.5 ma for compliant buffers (including cold sparing) in 3.3v range (vcc = 4.5v ) measured at vol = 2.4v io = 1.3 ma for compliant buffers (including cold sparing) in 3.0v range (vcc = 4.5v ) measured at vol = 2.4v io = 1.1 ma for compliant buffers (including cold sparing) in 2.5v range (vcc = 4.5v ) measured at vol = 2.0v table 6. 5v dc characteristics table 7. 2.5v lvds driver dc/ac characteristics symbol parameter test condition min. max. units comments t a operating temperature ? -55 125 c ? v dd supply voltage ? 2.3 2.7 v ? |vod| output differential voltage rload = 100 ? 230.7 446.5 mv see figure 4 vol output voltage low rload = 100 ? 1224 1817 mv see figure 4 voh output voltage high rload = 100 ? 993 1406 mv see figure 4 vos output offset voltage rload = 100 ? 1108 1610 mv see figure 4 |delta vod| change in |vod| between "0" and "1" rload = 100 ? 050mv ? |delta vos| change in |vos| between "0" and "1" rload = 100 ? 0100mv ? isa, isb output current drivers shorted to ground or vdd 1.0 6.3 ma ? isab output current drivers shorted together 2.4 4.8 ma ?
14 MH1RT 4110g ? aero ? 07/03 rbias bias resistor ? 9.8 10.2 k ? 1 per chip ibias bias static current ? 5.8 11.7 ma f max. maximum operating frequency vdd = 2.5v 0.2v ? 180 mhz consumption 14.8 ma clock clock signal duty cycle max. frequency 45 55 % ? tfall fall time 80-20% rload = 100 ? 669 1178 ps see figure 4 trise rise time 20-80% rload = 100 ? 670 1167 ps see figure 4 tp propagation delay rload = 100 ? 1270 2660 ps see figure 4 tsk1 duty cycle skew rload = 100 ? 0110ps ? ts k 2 channel to channel skew (same edge) rload = 100 ? 050ps ? table 7. 2.5v lvds driver dc/ac characteristics
15 MH1RT 4110g ? aero ? 07/03 applicable over recommended operating temperature and voltage range unless otherwise noted. table 8. 3v lvds driver dc/ ac characteristics symbol parameter test condition min. max. units comments t a operating temperature ? -55 125 c ? v dd supply voltage ? 2.7 3.3 v ? |vod| output differential voltage rload = 100 ? 244 462 mv see figure 4 vol output voltage low rload = 100 ? 1088 1775 mv see figure 4 voh output voltage high rload = 100 ? 828 1358 mv see figure 4 vos output offset voltage rload = 100 ? 958 568 mv see figure 4 |delta vod| change in |vod| between "0" and "1" rload = 100 ? 050mv ? |delta vos| change in |vos| between "0" and "1" rload = 100 ? 0150mv ? isa, isb output current drivers shorted to ground or vdd 1.0 6.3 ma ? isab output current drivers shorted together 2.6 5 ma ? rbias bias resistor ? 12.8 13.2 k ? 1 per chip ibias bias static current ? 6.513.8 ma ? f max. maximum operating frequency vdd = 3v 0.3v ? 200 mhz consumption 18.6 ma clock clock signal duty cycle max. frequency 45 55 % ? tfall fall time 80-20% rload = 10 ? 512 968 ps see figure 4 trise rise time 20-80% rload = 100 ? 512 970 ps see figure 4 tp propagation delay rload = 100 ? 1150 2300 ps see figure 4 tsk1 duty cycle skew rload = 100 ? 070ps ? ts k 2 channel to channel skew (same edge) rload = 100 ? 050ps ?
16 MH1RT 4110g ? aero ? 07/03 applicable over recommended operating temperature and voltage range unless otherwise noted. figure 4. test termination measurements table 9. 3.3v lvds driver dc/ ac characteristics symbol parameter test condition min. max. units comments t a operating temperature ? -55 125 c ? v dd supply voltage ? 33.6 v ? |vod| output differential voltage rload = 100 ? 251.4 452.2 mv see figure 4 vol output voltage low rload = 100 ? 1071 1731 mv see figure 4 voh output voltage high rload = 100 ? 804 1323 mv see figure 4 vos output offset voltage rload = 100 ? 937 1527 mv see figure 4 |delta vod| change in |vod| between "0" and "1" rload = 100 ? 050mv ? |delta vos| change in |vos| between "0" and "1" rload = 100 ? 0200mv ? isa, isb output current drivers shorted to ground or vdd 1.0 6.2 ma ? isab output current drivers shorted together 2.6 4.8 ma ? rbias bias resistor ? 16.3 16.7 k ? 1 per chip ibias bias static current ? 714.6 ma ? f max. maximum operating frequency vdd = 3.3v 0.3v ? 220 mhz consumption 14.8 ma clock clock signal duty cycle max. frequency 45 55 % ? tfall fall time 80-20% rload = 100 ? 445 838 ps see figure 4 trise rise time 20-80% rload = 100 ? 445 841 ps see figure 4 tp propagation delay rload = 100 ? 1120 2120 ps see figure 4 tsk1 duty cycle skew rload = 100 ? 080ps ? ts k 2 channel to channel skew (same edge) rload = 100 ? 050ps ? a b 100 ? vod vos va vb + () 2 -------------------------- =
17 MH1RT 4110g ? aero ? 07/03 figure 5. rise and fall measurements applicable over recommended operating temperature and voltage range unless otherwise noted. a b 100 ? 5 pf table 10. lvds receiver dc/ ac characteristics symbol parameter test condition min. max. units comments t a operating temperature ? -55 125 c ? v dd supply voltage ? 2.3 3.6 v ? vi input voltage range ? 02400mv ? vidth input differential voltage ? -100 +100 mv ? tp propagation delay cout = 50 pf, vdd = 2.5v 0.2v cout = 50 pf, vdd = 3.0v 0.3v cout = 50 pf, vdd = 3.3v 0.3v 0.9 0.7 0.7 3.5 2.7 2.4 ns ? tskew duty cycle distortion cout = 50 pf - 500 ps ? table 11. i/o buffers dc characteristics symbol parameter test condition typical units c in capacitance, input buffer (die) 3v 2.4 pf c out capacitance, output buffer (die) 3v 5.6 pf c i/o capacitance, bi-directional 3v 6.6 pf
18 MH1RT 4110g ? aero ? 07/03 testability techniques for complex designs, involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. the sheer size of complex designs and the num- ber of functional vectors that would need to be created to exercise them fully, strongly suggests the use of more efficient techniques. combinations of scan paths, multi- plexed access to memory and/or core blocks, and built-in-self-test logic must be employed, in addition to functional test patterns, to provide both the user and atmel the ability to test the finished product. an example of a highly complex design could include a pll for clock management or synthesis, a microcontroller or dsp engine or both, sram to support the microcontroller or dsp engine, and glue logic to support the interconnectivity of each of these blocks. the design of each of these blocks must take into consideration the fact that the manu- factured device will be tested on a high performance digital tester. combinations of parametric, functional, and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. the type of block dictates the type of testability technique to be employed. the pll will, by construction, provide access to key nodes so that functional and/or parametric test- ing can be performed. since a digital tester must control all the clocks during the testing of a gate array/embedded array, provision must be made for the vco to be bypassed. atmel ? s plls include a multiplexing capability for just this purpose. the addition of a few pins will allow other portions of the pll to be isolated for test, without impinging upon the normal functionality. in a similar vein, access to microcontroller, dsp, and sram blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. sram blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. multiplexing i/o pins provides a method for providing this accessibility. the glue logic can be designed using full scan techniques to enhance its testability. it should be noted that, in almost all of these cases, the purpose of the testability tech- nique is to provide atmel a means to assess the structural integrity of a gate array/embedded array, i.e., sort devices with manufacturing-induced defects. all of the techniques described above should be considered supplemental to a set of patterns which exercise the functionality of the design in its anticipated operating modes.
19 MH1RT 4110g ? aero ? 07/03 advanced packaging the MH1RT series are offered in ceramic packages: multi layers quad flat packs (mqfp) and a bga based on ceramic land grid arrays, so called multi layer column grid array (mcga). notes: 1. contact atmel local design centers to check the availability of the matrix/package combination. 2. four decks packages. table 12. packaging options package type (1) pin count mqfp (2) 196, 256 and 352 mcga (2) 349, 472 (1.27 mm pitch), and 576 (1 mm pitch)
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